Digital Electronics 

Section A
1. a) Prove the Demorgan’s laws using Boolean algebra.

2. a) Explain the working of master-slave JK flip flop. State its merit. What is Race problem in flip- flops?

b) Design a negative edge triggered T flip flop. The circuit has two inputs, T(toggle) and C(clock) and output Q and Q’. The output state is complemented if T=1 and the clock C changes from 1 to 0. Otherwise, under any other input condition, the output Q remains unchanged.

3. Differentiate between:
  i) Combinational and Sequential Logic Circuits. 

  ii) Synchronous and Asynchronous Counters

4. Do as directed:
   a) Conversion of 100.55 base 10 into binary, octal codes. 

b) Conversion of 1111010011011110 base 2 to decimal, hexadecimal.

5. a) Draw the circuit of a 3 to 8 decoder and explain its operation. How this can be used as a DEMUX. 

b) Design and explain Priority encoder

Section B
QUESTION 1
A Gray code is a sequence of codes which differ in one bit position at each step. For example 00, 01, 11, 10, 00 …is a two-bit Gray code. Design a counter made from JK flip-flops to produce a three-bit Gray code.

QUESTION 2
Mention the various A/D convertors. And Draw and discuss the circuit of a dual scope A/D convertor. Also discuss the comparison of advantages and disadvantages of each of A/D convertor.

QUESTION 3
Draw the circuit of a 4-bit shift registers and explains its operation. Also explain various different types of shift register with circuit diagram.

Section C

Question 1
What is the binary equivalent of the decimal number 68
  1001000 
  1000101 
  1001001 
  1000100 
 
Question 2
The Boolean expression 1+B+B is equivalent to
  B 
  1 
  A 
  0 
 
Question 3
counter consisting of four Flip-Flops will have maximum of ______ states
  4 
  32 
  16 
  8 
 
Question 4
The 2 s complement of the number 1101101 is
  101110 
  10011 
  111110 
  110010 
 
Question 5
Words having 8-bits are to be stored into computer memory. The number of lines required for writing into memory are
  1 
  2 
  8 
  16 
 
Question 6
The number of select lines for a 16 to 1 multiplexer is
  3 
  4 
  5 
  2 
 
Question 7
The output of three input AND gate will be low if the three inputs are
  0 0 0 
  1 1 0 
  1 1 1 
  0 0 1 
 
Question 8
Karnaugh map is used for the purpose of
  To map the given Boolean logic function. 
  Reducing the electronic circuits used. 
  To maximize the terms of a given a Boolean expression. 
  To minimize the terms in a Boolean expression. 
 
Question 9
A full adder logic circuit will have
  Two inputs and one output. 
  Three inputs and two outputs. 
  Two inputs and two outputs. 
  Three inputs and three outputs. 
 
Question 10
What kind of logic device or circuit is used to store information?
  Register 
  Gate 
  Inverter 
  Decoder 
 
Question 11
The digit F in hexadecimal system is equivalent to which decimal system?
  15 
  16 
  8 
  17 
 
Question 12
The excess-3 code of decimal 2 is represented by
  1001 
  1010 
  101 
  1001 
 
Question 13
DeMorgan s first theorem shows the equivalence of
  NAND gate and NOT gate 
  NOR gate and NAND gate. 
  NOR gate and Bubbled AND gate. 
  OR gate and Exclusive OR gate. 
 
Question 14
Scanner is a
  Output Device 
  Input device 
  Storage Device 
  None of the above 
 
Question 15
5 bit ripple adder can have ________ full adders
  16 
  32 
  4 
  5 
 
Question 16
A decade counter counts how many states
  10 
  11 
  9 
  16 
 
Question 17
Storage of 1KB means the following number of bytes
  1064 
  1000 
  1964 
  1024 
 
Question 18
How is a J-K flip-flop made to toggle?
  "J = 1, K = 1"
  "J = 1, K = 0"
  "J = 0, K = 1"
  "J = 0, K = 0"
 
Question 19
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
  cross coupling 
  low input voltages 
  gate impedance 
  asynchronous operation 
 
Question 20
The terminal count of a modulus-11 binary counter is ________.
  1000 
  1100 
  1010 
  1001 
 
Question 21
"The hexadecimal equivalent of 15,536 is"
  3BB0 
  3BB1 
  3CB1 
  3CB0 
 
Question 22
Why can a synchronous counter operate at a higher frequency than a ripple counter
  he flip-flops change one after the other. 
  None of the above 
  The flip-flops change at the same time. 
  A ripple counter is faster. 
 
Question 23
How many outputs are on a BCD decoder?
  4 
  16 
  8 
  10 
 
Question 24
One application of a digital multiplexer is to facilitate:
  parity checking 
  serial-to-parallel conversion 
  data selector 
  data generation 
 
Question 25
Convert BCD 0001 0010 0110 to binary
  1111000 
  1111101 
  1111110 
  1111100 
 
Question 26
Which gate is best used as a basic comparator?
  XOR 
  AND 
  NAND 
  NOT 
 
Question 27
Which of the following expressions is in the product-of-sums form?
  (AB)(CD) 
  (A + B)(C + D) 
  (AB)(CD) 
  AB + CD 
 
Question 28
Which of the following combinations cannot be combined into K-map groups?
  Overlapping combinations 
  Corners in the same column 
  Corners in the same row 
  Diagonal corners 
 
Question 29
"The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains"
  110 
  000101 
  00001 
  0001110 
 
Question 30
"With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in"
  40 µs
  40 ms 
  400 µs
  4µs
 
Question 31
The storage element for a static RAM is the
  FLIPFLOP 
  RESISTOR 
  DIODE 
  CAPACITOR 
 
Question 32
A 64-bit word consists of
  10 BYTES 
  4 BYTES 
  16 BYTES 
  8 BYTES 
 
Question 33
How many 2K × 8 ROM chips would be required to build a 16K × 8 memory system?
  16 
  8 
  4 
  2 
 
Question 34
Dynamic memory cells store a data bit in a
  DIODE 
  FLIP FLOP 
  CAPACITOR 
  RESISTOR 
 
Question 35
Which of the following is NOT a type of memory?
  ROM 
  RAM 
  FPROM 
  EEPROM 
 
Question 36
Which of the following memories is volatile?
  RAM 
  EROM 
  FLASH 
  ROM 
 
Question 37
Solve this BCD problem: 0100 + 0110 =
  00010111BCD 
  00010011BCD 
  00001011BCD 
  00010000BCD 
 
Question 38
The quantization error in an analog -to-digital converter can be reduced by:
  increasing the number of bits in the counter and DAC 
  decreasing the number of bits in the counter and DAC 
  increasing the number of bits in the counter and decreasing the number of bits in the DAC
  decreasing the number of bits in the counter and increasing the number of bits in the DAC
 
Question 39
The inverter can be produced with how many NAND gates?
  2 
  1 
  3 
  0 
 
Question 40
A full subtracter circuit requires
  two inputs and three outputs 
  three inputs and one output 
  three inputs and two outputs 
  two inputs and two outputs